1. abstract this application note provides interfacing solutions between some of the popular standard differential logic families and lvds technology. 2. introduction. lvds signals are differential signal technologies with a swing of 250 to 400mv and a dc offset of 1.2v. they are used today to interface between cmos and bicmos asics supplied with 3.3v or cell. lvds, lvpecl, pecl and ecl are all differential technologies but with different swings and offsets (see figure 1). figure 1: voltage levels this application note will show the possible interface between the lvds device and the other differential signal levels listed above. it will also give suggestions on how to interface supplied positive and negative devices. due to its speed capability, the application board requires a proper technical high speed layout, otherwise the system performance will be reduced. as a general guideline to get better performance from the pcb, the transmission striplines should be adapted as specified: - the input line must be routed away from the output lines or separated from the larger swings; - the lines must be as short as possible; - the termination line resistors must be the nearest to the receiver; - the use of surface mount components are recommended. pecl lvpecl ecl lvds february 2001 1/9 AN1318 application note interfacing between lvds and high speed differential logic families g. noviello
AN1318 - application note 2/9 3. overview of families. 3.1 lvds. lvds outputs always require a 100ohm load between the differential output because they work like a 100ohm current source of 3.2ma. this load also terminates the 50ohm controlled impedance line. lvds technology is not dependent on a specific power supply, meaning that there is an easy migration path to lower supply voltages, such as 3.3v or even 2.5v, while still maintaining the same performance. figure 2: lvds output configuration 3.2 ecl. this is the first differential high speed logic family ever introduced and one of todays fastest digital logics. however, the drawback of this technology is the negative voltage needed in relation to the actual supply voltage commonly used. ecl outputs are open emitter outputs, requiring a dc path with a more negative supply than vol. figure 3: ecl output configuration z=50 w z=50 w r=100 w lvds lvds v cc zo zo r3 ecl ecl vee r1 r2
AN1318 - application note 3/9 3.3 pecl. the positive supply voltage of this family is a remedy to the disadvantages of the negative supply voltage of ecl technology. the pecl technology works at 5v 5%, while for low voltage applications the lvpecl should be used, which has a 3.3v supply. figure 4: pecl output configuration 4. lvds family specifications. table 1: lvds driver dc characteristics (driver cells are terminated with 100ohm built-in) table 2: lvds receiver dc characteristics (receiver cells must be adapted with an external 100ohm) symbol parameter minimum maximum |vod| output diff voltage 250mv 450mv |vos| output offset 1125mv 1375mv d |vod| change in l vod l between 0 and 1 50mv d | vos| change in vos between 0 and 1 50mv |isa / isb| output current drivers shorted to gnd 24ma |isab| output current drivers shorted together 12ma ixa / ixb power off output leakage vcc=0v 1 m a symbol parameter minimum maximum vi input voltage range v ia or v ib 0v 2.4v vidth input differential threshold -0.100v 0.100v vhyst input differential hysteresis 0.025v z = 50 w and r = 220 w r = 100 w z z r2 lvpecl pecl vcc vcc r1 r1
AN1318 - application note 4/9 table 3: electrical characteristics comparison of the differential logic families 5. interfacing lvpecl to lvds. to accomplish lvpecl to lvds interfacing the pr oposal scheme uses the thevenin equation to fix the static level of the lvds input. the lvpecl differential output swing will surely go over the lvds input circuitry level. figure 5: lvpecl to lvds interfacing diagram this schematic is supplied by 3.3v, the termination of the transmission line z can be calculated with the thevenin equation. - the characteristic line impedance: - the dc condition for point a is vcc -2v symbol parameter lvds lvpecl pecl ecl vcc 3.3v 3.3v 5.0v gnd vee gnd gnd gnd -5.2v, -4.5v or -3.3v voh minimum output high level 1.250v 2.275v 3.975v -1.030v voh typical output high level 1.375v 2.345v 4.045v -0.955v voh maximum output high level 1.600v 2.420v 4.120v -0.880v vol minimum output low level 0.900v 1.490v 3.190v -1.810v vol typical output low level 1.025v 1.595v 3.295v -1.705v vol maximum output high level 1.250v 1.680v 3.380v -1.620v vcc = 3.3v lvpecl z z r1 r1 r2 r2 r3 r3 vcc = 3.3v lvds 3.3v a a b b zr 1 r 2 r 3 + () || =
AN1318 - application note 5/9 - the dc levels at the lvds input b are located within the lvds input common mode range the lvds input swing decreases depending on r2 and r3 6. interfacing lvds to lvpecl. direct interface is possible because of the common mode range of the lvpecl line receiver that is wide enough to process lvds signals. the differential input voltage range of the lvpecl line receivers are specified wide enough to process lvds signals. figure 6: lvds to lvpecl interfacing diagram 7. interfacing pecl to lvds. figure 7: interfacing pecl to lvds in the thevenin equation pointa r 1 () r 1 r 2 r 3 ++ () 2 v () vcc () = pointb r 3 () r 1 r 2 r 3 ++ () vil () vcc () = pointa vswing in pointb r 3 () r 2 r 3 + () * = vswing in vih 2.0 v < and vil 0 v > 3.3v 3.3v lvds lvpecl z = 50 w z = 50 w r 100 w vcc = 5v 3.3v r1 r1 r2 r2 r3 r3 pecl lvds z z a a b b vcc = 5v
AN1318 - application note 6/9 as described for lvpecl to interface from pecl to lvds a thevenin equation should be applied. the thevenin equation resistor terminates the transmission line z near the receiver. - the line characteristics impedance is: - the dc condition in point a is vcc - 2v - the dc levels at the lvds input b are located within the lvds input common mode range. the lvds input swing decreases depending on r2 and r3 8. interfacing lvds to pecl. the direct translation between lvds and pecl/l vpecl si gnals is not possible. this is because the lvds output common mode and differential voltage are not compatible with pecl input levels. devices like mc100(lv)el17 should be used to translate these signals. figure 8: interfacing lvds to pecl/lvpecl using the mc100(lv)el17 device 9. interfacing ecl to lvds. the ecc output requires a dc path to vee. the pull down resistors are connected to vee. the thevenin resistor pair represents the termination of the transmission line z (r1 || r2). for example, r1=270ohm and r2=75ohm making a parallel of 50ohm and generates a dc level of 1.2v in the static entry point of the lvds circuitry. figure 9: interfacing ecl to lvds zr 1 r 2 r 3 + () || = pointa r 1 () r 1 r 2 r 3 ++ () 2 v () vcc () = pointb r 3 () r 1 r 2 r 3 ++ () vil () vcc () = pointa in pointb r 3 () r 2 r 3 + () * vswing = in vswing 3.3v 5v z = 50 w lvds mc100(lv)el17 z = 50 w r 100 w to pecl z = 50 w ecl 3.3v lvd s 3.3v vee vee r1 270 w 10 pf 10 pf z = 50 w r2 75 w r1 270 w r2 75 w
AN1318 - application note 7/9 note: in the board layout both parallel resistor terminations should be located as close as possible to the coupling capacitors. 10. interfacing lvds to ecl. figure 10: interfacing lvds to ecl dc voltage can be generated with a resistor divider depending on the vcc value. examples: vcc=gnd and vee=-5v => r1=1.2kohm and r2=3.4kohm vcc=gnd and vee=-3.3v => r1=680ohm and r2=1kohm note: in the board layout for both interfaces the resistors and capacitors should be located as close as possible to the ecl input. 11. capacitive coupling lvds to ecl. several ecl devices supply a vbb (vbb~vcc-1.3v) reference voltage. it can be used for differential capacitive coupling. the 100kohm gives stable determined output states during null signal conditions. figure 11: capacitive coupling lvds to ecl using vbb lv ds 3.3v ecl r1 r2 r2 10 pf 10 pf r1 z = 50 w z = 50 w 100 w vcc vee lvds ecl vcc z=50 w z=50 w 100 w 10pf 10pf 1k w 1k w 20k w to 100k w vbb 10nf
AN1318 - application note 8/9 12. capacitive coupling ecl to lvds using vos reference voltage. some devices with lvds interfaces supply vos reference voltage, like the stlvd111. this can be used for capacitive coupling. when the transmission line length is very short, a parallel termination should be used and replaced as close as possible to the coupling capacitors. figure 12: capacitive coupling ecl to lvds using vos reference voltage ecl lvds 3.3v z=50 w z=50 w 10pf 10pf 1k w 1k w vos=1.2v 100k w vtt 50 w 50 w
AN1318 - application note 9/9 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specification mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is a trademark of stmicroelectronics ? 2001 stmicroelectronics - printed in italy - all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com
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